VL4351 VLSI Signal Processing Syllabus:

VL4351 VLSI Signal Processing Syllabus – Anna University PG Syllabus Regulation 2021

COURSE OBJECTIVES:

 To introduce techniques for altering existing DSP structures to suit VLSI implementations.
 To introduce efficient design of DSP architectures suitable for VLSI.

UNIT I INTRODUCTION TO DSP SYSTEMS, PIPELINING AND PARALLEL PROCESSING OF FIR FILTERS

Introduction to DSP systems – typical DSP algorithms, data flow and dependence graphs – critical path, loop bound, iteration bound, longest path matrix algorithm, pipelining and parallel processing of FIR filters, pipelining and parallel processing for low power.

UNIT II RETIMING, ALGORITHMIC STRENGTH REDUCTION

Retiming – definitions and properties, unfolding – an algorithm for unfolding, properties of unfolding, sample period reduction and parallel processing application, algorithmic strength reduction in filters and transforms – 2-parallel FIR filter, 2-parallel fast FIR filter, DCT architecture, rank-order filters, Odd-Even, Merge-Sort architecture, parallel rank-order filters.

UNIT III FAST CONVOLUTION, PIPELINING AND PARALLEL PROCESSING OF IIR FILTERS

Fast convolution – Cook-Toom algorithm, modified Cook-Toom algorithm, Pipelined and parallel recursive filters – Look-Ahead pipelining in first-order IIR filters, Look-Ahead pipelining with powerof-2 decomposition, Clustered look-ahead pipelining, Parallel processing of IIR filters, combined pipelining and parallel processing of IIR filters.

UNIT IV BIT-LEVEL ARITHMETIC ARCHITECTURES

Bit-level arithmetic architectures – parallel multipliers with sign extension, parallel carry-ripple and carry-save multipliers, design of lyon‟s bit-serial multipliers using Horner‟s rule, bit-serial FIR filter, CSD representation, CSD multiplication using Horner‟s rule for precision improvement, Distributed Arithmetic fundamentals and FIR filters

UNIT V NUMERICAL STRENGTH REDUCTION, SYNCHRONOUS AND ASYNCHRONOUS PIPELINING

Numerical strength reduction – sub-expression elimination, multiple constant multiplication, iterative matching, synchronous pipelining and clocking styles, clock skew in edge triggered single phase clocking, two-phase clocking, wave pipelining. Asynchronous pipelining – Bundled Data versus Dual-Rail protocol.

TOTAL:45 PERIODS

COURSE OUTCOMES:

CO1:Ability to determine the parameters influencing the efficiency of DSP architectures and apply pipelining and parallel processing techniques to alter FIR structures for efficiency
CO2:Ability to analyse and modify the design equations leading to efficient DSP architectures for transforms apply low power techniques for low power dissipation
CO3:Ability to speed up convolution process and develop fast and area efficient IIR structures
CO4:Ability to develop fast and area efficient multiplier architectures
CO5:Ability to reduce multiplications and build fast hardware for synchronous digital systems

REFERENCES

1. Keshab K. Parhi, “ VLSI Digital Signal Processing Systems, Design and Implementation “, Wiley, Interscience, 2007
2. U. Meyer – Baese, “ Digital Signal Processing with Field Programmable Gate Arrays”, Springer, 2nd Edition, 2004.