VL4251 Design for Verification Using UVM Syllabus:

VL4251 Design for Verification Using UVM Syllabus – Anna University PG Syllabus Regulation 2021

COURSE OBJECTIVES:

 To provide the students complete understanding on UVM testing
 To become proficient at UVM verification,
 To provide an experience on self checking UVM test benches

UNIT I INTRODUCTION

Overview- The Typical UVM Test bench Architecture- The UVM Class Library-Transaction-Level Modeling (TLM) -Overview- TLM, TLM-1, and TLM-2.0 -TLM-1 Implementation- TLM-2.0 Implementation

UNIT II DEVELOPING REUSABLE VERIFICATION COMPONENTS

Modeling Data Items for Generation – Transaction-Level Components – Creating the Driver – Creating the Sequencer – Connecting the Driver and Sequencer -Creating the Monitor – Instantiating Components- Creating the Agent – Creating the Environment -Enabling Scenario Creation -Managing of Test-Implementing Checks and Coverage

UNIT III UVM USING VERIFICATION COMPONENTS

Creating a Top-Level Environment- Instantiating Verification Components – Creating Test Classes -Verification Component Configuration – Creating and Selecting a User-Defined Test – Creating Meaningful Tests- Virtual Sequences- Checking for DUT Correctness- Scoreboards Implementing a Coverage Model

UNIT IV UVM USING THE REGISTER LAYER CLASSES

Using The Register Layer Classes – Back-Door Access -Special Registers -Integrating a Register- Model in a Verification Environment- Integrating a Register Model- Randomizing Field Values- Pre-Defined Sequences

UNIT V ASSIGNMENT IN TESTBENCHES

Assignment, APB: Protocol, Test bench Architecture, Driver and Sequencer, Monitor, Agent and Env; Creating Sequences, Building Test, Design and Testing of Top Module.

TOTAL: 45 PERIODS

COURSE OUTCOMES:

At the end of the course, students will be able to
CO1:understand the basic concepts of two methodologies UVM
CO2:build actual verification components.
CO3:generate the register layer classes.
CO4:code testbenches using UVM.
CO5:understand advanced peripheral bus testbenches.

REFERENCES

1. The UVM Primer, An Introduction to the Universal Verification Methodology, Ray Salemi, 2013.
2. SystemVerilog for Verification: A Guide to Learning the Testbench Language Features, Chris Spear, Greg Tumbush, 3rd edition, 2012.
3. https://www.udemy.com/learn-ovm-UVM/ 2.
4. http://www.testbench.in/ut_00_index.html 3.
5. http://www.testbench.in/ot_00_index.html
6. https://www.accellera.org/images/downloads/standards/UVM/UVM_users_guide_1.2.pdf