VL4211 Verification using UVM Laboratory Syllabus:

VL4211 Verification using UVM Laboratory Syllabus – Anna University PG Syllabus Regulation 2021

COURSE OBJECTIVES:

 to help the engineers to design the system with verilog and system Verilog
 Complete understanding of Verilog Hardware Description Language
 to practice for writing synthesizable RTL models that work correctly in both simulation and synthesis.

LIST OF EXPERIMENTS

1. Simulate a simple UVM testbench and DUT
2. Examining the UVM testbench
3. Design and simulate sequence items and sequence
4. Design and simulate a UVM driver and sequencer
5. Design and simulating UVM monitor and agent
6. Design, simulate and examine coverage
7. Design and simulate a UVM scoreboard and environment, and verifying the outputs of a (faulty) DUT
8. Design and simulate a test that runs multiple sequence
9. Design and simulate a configurable UVM test environment

TOTAL: 60 PERIODS

COURSE OUTCOMES:

On successful completion of this course, students will be able to
CO1: understand the features and capabilities of the UVM class library for system Verilog
CO2: combine multiple UVCs into a complete verification environment
CO3:create and configure reusable, scalable, and robust UVM verification components (UVCs)
CO4: create a UVM testbench structure using the UVM library base classes and the UVM factory
CO5:develop a register model for your DUT and use the model for initialization and accessing DUT registers

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