VL4112 Analog IC Design Laboratory Syllabus:
VL4112 Analog IC Design Laboratory Syllabus – Anna University PG Syllabus Regulation 2021
COURSE OBJECTIVES:
Carry out a detailed analog circuit design starting with transistor characterization and finally
realizing an IA design.
At various stages of design, exposure to state of art CAD VLSI tool in various phases of
experiments designed to bring out the key aspects of each important module in the CAD tool
including the simulation, layout, LVS and parasitic extracted simulation.
LIST OF EXPERIMENTS
1. Extraction of process parameters of CMOS process transistors
a. Plot ID vs. VGS at different drain voltages for NMOS, PMOS.
b. Plot ID vs. VGS at particular drain voltage for NMOS, PMOS and determine Vt.
c. Plot log ID vs. VGS at particular gate voltage for NMOS, PMOS and determine IOFF and subthreshold slope.
d. Plot ID vs. VDS at different gate voltages for NMOS, PMOS and determine Channel length modulation factor.
e. Extract Vth of NMOS/PMOS transistors (short channel and long channel). Use VDS of appropriate voltage To extract Vth use the following procedure.
i. Plot gm vs VGS using SPICE and obtain peak gm point.
ii. Plot y=ID/(gm) as a function of VGS using SPICE.
iii. Use SPICE to plot tangent line passing through peak gm point in y (VGS) plane and determine Vth.
f. Plot ID vs. VDS at different drain voltages for NMOS, PMOS, plot DC load line and calculate gm, gds, gm/gds, and unity gain frequency. Tabulate result according to technologies and comment on it.
2. CMOS inverter design and performance analysis
a. i. Plot VTC curve for CMOS inverter and thereon plot dVout vs. dVin and determine transition voltage and gain g. Calculate VIL, VIH, NMH, NML for the inverter.
ii. Plot VTC for CMOS inverter with varying VDD.
iii. Plot VTC for CMOS inverter with varying device ratio.
b. Perform transient analysis of CMOS inverter with no load and with load and determine propagation delay tpHL, tpLH, 20%-to-80% rise time tr and 80%-to-20% fall time tf.
c. Perform AC analysis of CMOS inverter with fanout 0 and fanout 1.
3. Use spice to build a three stage and five stage ring oscillator circuit and compare its frequencies. Use FFT and verify the amplitude and frequency components in the spectrum.
4. Single stage amplifier design and performance analysis
a. Plot small signal voltage gain of the minimum-size inverter in the technology chosen as a function of input DC voltage. Determine the small signal voltage gain at the switching point using spice and compare the values for two different process transistors.
b. Consider a simple CS amplifier with active load, with NMOS transistor as driver and PMOS transistor as load.
i. Establish a test bench to achieve VDSQ=VDD/2.
ii. Calculate input bias voltage for a given bias current.
iii. Use spice and obtain the bias current. Compare with the theoretical value
iv. Determine small signal voltage gain, -3dB BW and GBW of the amplifier
v. using small signal analysis in spice, considering load capacitance.
vi. Plot step response of the amplifier with a specific input pulse amplitude.
vii. Derive time constant of the output and compare it with the time constant
viii. resulted from -3dB Band Width.
ix. Use spice to determine input voltage range of the amplifier
5. Three OPAMP Instrumentation Amplifier (INA). Use proper values of resistors to get a three OPAMP INA with differential-mode voltage gain=10. Consider voltage gain=2 for the first stage and voltage gain=5 for the second stage.
i. Draw the schematic of op-amp macro model.
ii. Draw the schematic of INA.
iii. Obtain parameters of the op-amp macro model such that it meets a given specification for:
i.low-frequency voltage gain,
ii.unity gain BW (fu),
iii.input capacitance,
iv.output resistance,
v.CMRR
d. Draw schematic diagram of CMRR simulation setup.
e. Simulate CMRR of INA using AC analysis (it’s expected to be around 6dB below CMRR of OPAMP).
f. Plot CMRR of the INA versus resistor mismatches (for resistors of second stage only) changing from -5% to +5% (use AC analysis). Generate a separate plot for mismatch in each resistor pair. Explain how CMRR of OPAMP changes with resistor mismatches.
g. Repeat (iii) to (vi) by considering CMRR of all OPAMPs with another low frequency gain setting.
6. Use Layout editor.
a. Draw layout of a minimum size inverter using transistors from CMOS process library. Use Metal 1 as interconnect line between inverters.
b. Run DRC, LVS and RC extraction. Make sure there is no DRC error.
c. Extract the netlist. Use extracted netlist and obtain tPHLtPLH for the inverter using Spice.
d. Use a specific interconnect length and connect and connect three inverters in a chain.
e. Extract the new netlist and obtain tPHL and tPLH of the middle inverter.
f. Compare new values of delay times with corresponding values obtained in part ‘c’.
7. Design a differential amplifier with resistive load using transistors from CMOS process library that meets a given specification for the following parameter
a. low-frequency voltage gain,
b. unity gain BW (fu),
c. Power dissipation
i. Perform DC analysis and determine input common mode range and compare with the theoretical values.
ii. Perform time domain simulation and verify low frequency gain.
iii. Perform AC analysis and verify.
TOTAL: 60 PERIODS
COURSE OUTCOMES:
On successful completion of this course, students will be able to
CO1: Design digital and analog Circuit using CMOS given a design specification.
CO2: Design and carry out time domain and frequency domain simulations of simple analog building blocks, study the pole zero behaviors and compute the input/output impedances
CO3: Use EDA tools for Circuit Design