VL4111 FPGA Laboratory Syllabus:

VL4111 FPGA Laboratory Syllabus – Anna University PG Syllabus Regulation 2021

COURSE OBJECTIVES:

 To help engineers read, understand, and maintain digital hardware models and conventional verification test benches written in Verilog and System Verilog.
 To provide a critical language foundation for more advanced training on System Verilog

LIST OF EXPERIMENTS

1. Introduction to Verilog and System Verilog
2. Running simulator and debug tools
3. Experiment with 2 state and 4 state data types
4. Experiment with blocking and non-blocking assignments
5. Model and verify simple ALU
6. Model and verify an Instruction stack
7. Use an interface between testbench and DUT
8. Developing a test program
9. Create a simple and advanced OO testbench
10. Create a scoreboard using dynamic array
11. Use mailboxes for verification
12. Generate constrained random test values
13. Using coverage with constrained random tests

TOTAL: 60 PERIODS

COURSE OUTCOMES:

On successful completion of this course, students will be able to
CO1:Understand and use the System Verilog RTL design and synthesis features, including new data types, literals, procedural blocks, statements, and operators, relaxation of Verilog language rules, fixes for synthesis issues, enhancements to tasks and functions, new hierarchy and connectivity features, and interfaces.
CO2:Appreciate and apply the System Verilog verification features, including classes, constrained random stimulus, coverage, strings, queues and dynamic arrays, and learn how to utilize these features for more effective and efficient verification.
CO3: The implementation of higher level of abstraction to design and verification
CO4: Develop Verilog test environments of significant capability and complexity.
CO5: Integrate scoreboards, multichannel sequencers and Register Models