VL4091 Network on Chip Syllabus:

VL4091 Network on Chip Syllabus – Anna University PG Syllabus Regulation 2021

COURSE OBJECTIVES:

The students should be made to:
 Understand the concept of Network – on – Chip
 Learn router architecture designs
 Study fault tolerance Network – on – Chip

UNIT I INTRODUCTION TO NOC

Introduction to NOC – OSI Layer Rules in NOC – Interconnection Networks in Network-On-Chip Network Topologies – Switching Techniques – Routing Strategies – Flow Control Protocol Quality of-Service Support

UNIT II ARCHITECTURE DESIGN

Switching Techniques and Packet Format – Asynchronous FIFO Design – GALS Style of Communication – Wormhole Router Architecture Design – VC Router Architecture Design – Adaptive Router Architecture Design

UNIT III ROUTING ALGORITHM

Packet Routing-QOS, Congestion Control and Flow Control – Router Design – Network Link Design – Efficient and Deadlock-Free Tree-Based Multicast Routing Methods – Path-Based Multicast Routing For 2D and 3D Mesh Networks- Fault-Tolerant Routing Algorithms – Reliable and Adaptive Routing Algorithms

UNIT IV TEST AND FAULT TOLERANCE OF NOC

Design-Security in Networks-On-Chips-Formal Verification of Communications in Networks-On Chips-Test and Fault Tolerance For Networks-On-Chip Infrastructures-Monitoring Services For Networks-On-Chips

UNIT V THREE-DIMENSIONAL INTEGRATION OF NETWORK-ON-CHIP

Three-Dimensional Networks-On-Chips Architectures – A Novel Dimensionally-Decomposed Router for On-Chip Communication in 3D Architectures – Resource Allocation For QOS On-Chip Communication – Networks-On-Chip Protocols-On-Chip Processor Traffic Modeling For Networks On-Chip

TOTAL:45 PERIODS

COURSE OUTCOMES:

At the end of this course, the students will be able to:
CO1:Compare different architecture design
CO2:Discuss different routing algorithms
CO3:Explain three dimensional Networks on Chip architectures
CO4:Test and design fault tolerant NOC
CO5:Design three dimensional architectures of NOC

REFERENCES

1. Chrysosto MOSnicopoulos, Vijaykrishnan Narayanan, Chita R.Das” Networks-On – Chip “ Architectures Holistic Design Exploration”, Springer.
2. Fayezgebali, Haythamelmiligi, Hqhahedwatheq E1-Kharashi “Networks-On-Chips Theory and Practice CRC Press
3. Konstantinos Tatas and Kostas Siozios “Designing 2D and 3D Network-On-Chip Architectures” 2013
4. Palesi, Maurizio, Daneshtalab, Masoud “Routing Algorithms in Networks-On-Chip” 2014