VL4071 ASIC Design Syllabus:
VL4071 ASIC Design Syllabus – Anna University PG Syllabus Regulation 2021
COURSE OBJECTIVES:
To Focus on the Semi-Custom IC Design and introduces the Principles of Design Logic Cells, I/O Cells and Interconnect Architecture, with Equal Importance given to FPGA and ASIC styles.
To deal with the entire FPGA and ASIC Design Flow from the Circuit and Layout Design Point of View
UNIT I INTRODUCTION TO ASICS, CMOS LOGIC AND ASIC LIBRARY DESIGN
Types of Asics – Design Flow – CMOS Transistors – Combinational Logic Cell – Sequential Logic Cell – Data Path Logic Cell – Transistors as Resistors – Transistor Parasitic Capacitance- Logical Effort.
UNIT II PROGRAMMABLE ASICS, PROGRAMMABLE ASIC LOGIC CELLS AND PROGRAMMABLE ASIC I/O CELLS
Anti Fuse – Static Ram – EPROM and EEPROM Technology – ACTEL ACT- Xilinx LCA –ALTERA FLEX – ALTERA MAX DC & AC Inputs and Outputs – Clock & Power Inputs – Xilinx I/O Blocks.
UNIT III PROGRAMMABLE ASIC ARCHITECTURE
Architecture and Configuration of ARTIX / Cyclone and KINTEX Ultra Scale / STRATIX FPGA – Micro-Blaze / NIOS Based Embedded Systems – Signal Probing Techniques.
UNIT IV LOGIC SYNTHESIS, PLACEMENT AND ROUTING
Logic Synthesis – Floor Planning Goals and Objectives, Measurement of Delay in Floor Planning, Floor Planning Tools, I/O and Power Planning, Clock Planning, Placement Algorithms. Routing: Global Routing, Detailed Routing, Special Routing.
UNIT V SYSTEM-ON-CHIP DESIGN
SoC Design Flow, Platform-Based and IP Based SoC Designs, Basic Concepts of Bus-Based Communication Architectures, High Performance Filters using Delta-Sigma Modulators. Case Studies: Digital Camera, SDRAM, High Speed Data standards.
TOTAL :45 PERIODS
COURSE OUTCOMES:
At the end of this course, the students will be
CO1: able to apply Logical Effort Technique for predicting Delay, Delay Minimization and FPGA Architectures
CO2: able to Design Logic Cells and I/O Cells
CO3: able to analyze the various resources of recent FPGAs
CO4: able to use Algorithms for Floor Planning and Placement of Cells and to Apply Routing Algorithms for Optimization of Length and Speed.
CO5: able to analyze High Performance Algorithms Available for ASICs
REFERENCES
1. M.J.S.Smith, “Application Specific Integrated Circuits”, Pearson, 2003.
2. Steve Kilts, “Advanced FPGA Design,” Wiley Inter-Science,2006
3. Roger Woods, John Mcallister, Dr. Ying Yi, Gaye Lightbod, “FPGA-Based Implementation of Signal Processing Systems”, Wiley, 2008.