VL4010 System Verilog Syllabus:
VL4010 System Verilog Syllabus – Anna University PG Syllabus Regulation 2021
COURSE OBJECTIVES:
Insight to Apply System Verilog Concepts to Do Synthesis, Analysis and Architecture Design.
Understanding of System Verilog and SVA for Verification and Understand The Improvements in Verification Efficiency.
Understand Advanced Verification Features, Such As The Practical Use of Classes, Randomization, Checking, and Coverage.
Knowledge to Communicate The Purpose and Results of a Design Experiment in Written and Oral
Understand The Purpose of Hardware-Software Verification
UNIT I VERIFICATION METHODOLOGY
Verification Guidelines: Introduction, Verification Process, Verification Plan, Verification Methodology Manual, Basic Testbench Functionality, Directed Testing, Methodology Basics, Constrained-Random Stimulus, Functional Coverage, Testbench Components, Layered Testbench
UNIT II SYSTEM VERILOG BASICS AND CONCEPTS
Data Types: Built-in Data Types, Fixed-Size Arrays, Dynamic Arrays, Queues, Creating New Types With Typedef, Creating User-Defined Structures, Enumerated Types, Constants, Strings. Procedural Statements and Routines: Procedural Statements, Tasks, Functions, and Void Functions
UNIT III OOPS
Introduction-Where to Define a Class- OOPS Terminology -Creating New Objects -Object Deallocation- Using Objects -Static Variables Vs. Global Variables -Class Routines -Defining Routines Outside of The Class – Scoping Rules -Using One Class Inside Another – Understanding Dynamic Objects -Copying Objects -Public Vs. Private -Straying Off Course – Building a Testbench
UNIT IV THREADS AND INTER-PROCESS COMMUNICATION AND FUNCTIONAL COVERAGE
Working With Threads, Inter-Process Communication, Events, Semaphores, Mailboxes, Building a Test bench With Threads and IPC. Coverage Types, Functional Coverage Strategies, Simple Functional Coverage Example, Coverage Options, Parameterized Cover Groups, Analysing Coverage Data, Measuring Coverage Statistics
UNIT V COMPLETE DESIGN MODEL USING SYSTEM VERILOG- CASE STUDY
System Verilog ATM Example, Data Abstraction, Interface Encapsulation, Design Top Level Squat, Receivers and Transmitters, Test Bench for ATM.
TOTAL:45 PERIODS
PRACTICAL EXERCISES: 30 PERIODS
1. Design a Test bench for 2×1 Mux Using Gates
2. Implementation of a Mailbox By Allocating Memory
3. Implementation and Testing of Semaphore for a Simple DUT
4. Implementation of Scoreboard for a Simple DUT
TOTAL:45+30=45 PERIODS
COURSE OUTCOMES:
Upon completion of this course, students should demonstrate the ability to
CO1: use system 63erilog to create correct, efficient, and re-usable models for digital designs
CO2: use system 63erilog to create testbenches for digital designs
CO3: understand and effectively exploit new constructs in System Verilog for verification
CO4: understand the communication between modules
CO5: designing a complete system model using Verilog
REFERENCES
1. System Verilog for Verification: a Guide to Learning The Testbench Language Features, Chris Spear, Springer 2006
2. Writing Testbenches: Functional Verification of HDL Models, Second Edition, Janick Bergeron, Kluwer Academic Publishers, 2003.
3. System Verilog for Design: a Guide to Using System Verilog for Hardware Design and Modeling, 2nd Edition, Stuart Sutherland, Simon Davidman and Peter Flake, Springer
4. Open Verification Methodology Cookbook, Mark Glasser, Springer, 2009
5. Assertion-Based Design, 2nd Edition, Harry D. Foster, Adam C. Krolnik, David J. Lacey, Kluwer Academic Publishers, 2004