VE4201 FPGA System Design Syllabus:
VE4201 FPGA System Design Syllabus โ Anna University PG Syllabus Regulation 2021
COURSE OBJECTIVES:
๏ท Students can understand the concepts of FPGA and the need for FPGA in embedded.
๏ท the course is to provide a thorough understanding about and hands-on practice with FPGA based digital system design and emulation
๏ท To make the student learn, FPGA fundamentals, design and implementation of Circuits In Them
๏ท Understanding the Role of FPGAs and ASIC In Embedded Systems
UNIT I FPGA ARCHITECTURE AND OVERVIEW
Embedded System Design Flow โ Robot Control System โ Digital Design Platforms โ Microprocessor Based Design โ Single-Chip Computer/Microcontroller-Based Design โ Application Specific Standard Products (ASSPs) โ Design Using FPGA โ Robotic Rover Application โ FPGA Devices โ FPGA and CPLD โ Architecture of a Spartan-3 ETM FPGA โ Floor Plan and Routing โ Timing Model for a FPGA โ FPGA Power Usage.
UNIT II EMBEDDED SYSTEM DESIGN
FPGA-Based Embedded Processor โ Design Re-Use Using On-Chip Bus Interface โ Creating a Customized Microcontroller โ Robot Axis Position Control โ FPGA-Based Signal Interfacing And Conditioning โ Motor Control Using FPGA- Case Studies for Motor Control -Prototype using FPGAFPGA Design Test Methodology
UNIT III VERILOG CONSTRUCTS
VLSI Design Flow- Behavioral Style, the Dataflow Style, And Structural Style โ Data Types โ Constants โ Assignment Statement โ Operators โ Conditional Expressions โ Statement Types โ Vector Operations โ Bit Selects โ Functions โ Gate Level Modeling
UNIT IV VERILOG MODELING COMBINATIONAL CIRCUITS
Combinational Logic -Adders โ Multiplexers โ Decoders -Comparator -Parity Generators ALU โ Three State Gate โ UART Model.
UNIT V VERILOG MODELLING SEQUENTIAL CIRCUITS
Modelling Latches and Flip Flopsโ Sequential Logic โ Memory โ Registers-Counters Modeling FSM Design Synchronous And Asynchronous โ Shift Register- Test Bench Verification. Stepper Motor Control, Servo Motor Control.
TOTAL:45 PERIODS
PRACTICAL EXERCISES: 30 PERIODS
1. Design Entry Using VHDL Or Verilog Using HDL Languages of
I. Combinational Circuits Namely 8:1 Mux/Demux, Full Adder, 8-Bit Magnitude Comparator, Encoder/Decoder, Priority Encoder.
II. Sequential Circuits Namely D-FF, 4-Bit Shift Registers (SISO, SIPO, PISO, Bidirectional), 3-Bit Synchronous Counters.
2. Test Vector Generation And Timing Analysis of Sequential And Combinational Logic Design for exercise (1) above.
3. Synthesis, P&R And Post P&R Simulation of the Components Simulated In (1) Above.
4. FPGA Implementation of PCI Bus & Arbiter. .
5. Verifying Design Functionality Using Either Chipscope Feature (Xilinx) /the Signal Tap Feature (Altera)/Other Equivalent Feature . Invoke the PLL And Demonstrate the Use of the PLL Module for Clock Generation in FPGAs.
TOTAL:45+30=75 PERIODS
COURSE OUTCOMES:
CO1: students can learn the concepts of FPGA.
CO2: students can design embedded system with appropriate FPGA based on applications
CO3: students can write verilog code for combinational and sequential logics
CO4: students can design a combinational circuit using Verilog.
CO5: students can use FPGA EDA tools for design and analysis.
REFERENCES
1. Rahul Dubey, โIntroduction to Embedded System Design Using Field Programmable Gate Arraysโ Springer-Verlag London Limited, 2009
2. John F. Wakerly, Digital Design Principles And Practicesโ, Pearson Education, Asia, Iii Edition, 2003.
3. Blaine Readler, โVerilog By Example: a Concise Introduction for FPGA Designโ, Full ARC Press,2011.
4. J. Bhasker, โa Verilog HDL Primer, Third Edition Hardcoverโ, Star Galaxy Publishing; 3rd Edition, 2005
5. J.Bhasker, โVerilog HDL Synthesis, a Practical Primerโ, Star Galaxy Publishing; 3rd Edition,1998.