VE4201 FPGA System Design Syllabus:

VE4201 FPGA System Design Syllabus – Anna University PG Syllabus Regulation 2021

COURSE OBJECTIVES:

 Students can understand the concepts of FPGA and the need for FPGA in embedded.
 the course is to provide a thorough understanding about and hands-on practice with FPGA based digital system design and emulation
 To make the student learn, FPGA fundamentals, design and implementation of Circuits In Them
 Understanding the Role of FPGAs and ASIC In Embedded Systems

UNIT I FPGA ARCHITECTURE AND OVERVIEW

Embedded System Design Flow – Robot Control System – Digital Design Platforms – Microprocessor Based Design – Single-Chip Computer/Microcontroller-Based Design – Application Specific Standard Products (ASSPs) – Design Using FPGA – Robotic Rover Application – FPGA Devices – FPGA and CPLD – Architecture of a Spartan-3 ETM FPGA – Floor Plan and Routing – Timing Model for a FPGA – FPGA Power Usage.

UNIT II EMBEDDED SYSTEM DESIGN

FPGA-Based Embedded Processor – Design Re-Use Using On-Chip Bus Interface – Creating a Customized Microcontroller – Robot Axis Position Control – FPGA-Based Signal Interfacing And Conditioning – Motor Control Using FPGA- Case Studies for Motor Control -Prototype using FPGAFPGA Design Test Methodology

UNIT III VERILOG CONSTRUCTS

VLSI Design Flow- Behavioral Style, the Dataflow Style, And Structural Style – Data Types – Constants – Assignment Statement – Operators – Conditional Expressions – Statement Types – Vector Operations – Bit Selects – Functions – Gate Level Modeling

UNIT IV VERILOG MODELING COMBINATIONAL CIRCUITS

Combinational Logic -Adders – Multiplexers – Decoders -Comparator -Parity Generators ALU – Three State Gate – UART Model.

UNIT V VERILOG MODELLING SEQUENTIAL CIRCUITS

Modelling Latches and Flip Flops– Sequential Logic – Memory – Registers-Counters Modeling FSM Design Synchronous And Asynchronous – Shift Register- Test Bench Verification. Stepper Motor Control, Servo Motor Control.

TOTAL:45 PERIODS

PRACTICAL EXERCISES: 30 PERIODS

1. Design Entry Using VHDL Or Verilog Using HDL Languages of
I. Combinational Circuits Namely 8:1 Mux/Demux, Full Adder, 8-Bit Magnitude Comparator, Encoder/Decoder, Priority Encoder.
II. Sequential Circuits Namely D-FF, 4-Bit Shift Registers (SISO, SIPO, PISO, Bidirectional), 3-Bit Synchronous Counters.
2. Test Vector Generation And Timing Analysis of Sequential And Combinational Logic Design for exercise (1) above.
3. Synthesis, P&R And Post P&R Simulation of the Components Simulated In (1) Above.
4. FPGA Implementation of PCI Bus & Arbiter. .
5. Verifying Design Functionality Using Either Chipscope Feature (Xilinx) /the Signal Tap Feature (Altera)/Other Equivalent Feature . Invoke the PLL And Demonstrate the Use of the PLL Module for Clock Generation in FPGAs.

TOTAL:45+30=75 PERIODS

COURSE OUTCOMES:

CO1: students can learn the concepts of FPGA.
CO2: students can design embedded system with appropriate FPGA based on applications
CO3: students can write verilog code for combinational and sequential logics
CO4: students can design a combinational circuit using Verilog.
CO5: students can use FPGA EDA tools for design and analysis.

REFERENCES

1. Rahul Dubey, “Introduction to Embedded System Design Using Field Programmable Gate Arrays” Springer-Verlag London Limited, 2009
2. John F. Wakerly, Digital Design Principles And Practices”, Pearson Education, Asia, Iii Edition, 2003.
3. Blaine Readler, “Verilog By Example: a Concise Introduction for FPGA Design”, Full ARC Press,2011.
4. J. Bhasker, “a Verilog HDL Primer, Third Edition Hardcover”, Star Galaxy Publishing; 3rd Edition, 2005
5. J.Bhasker, “Verilog HDL Synthesis, a Practical Primer”, Star Galaxy Publishing; 3rd Edition,1998.