VE4001 Parallel and Reconfigurable Architectures Syllabus:
VE4001 Parallel and Reconfigurable Architectures Syllabus – Anna University PG Syllabus Regulation 2021
COURSE OBJECTIVE:
To Educate the Students to the Fundamentals of Parallel Processing
To Teach the Fundamentals of Network Topologies for Multiprocessors
To Introduce Different Pipeline Designs
To Introduce Features of Parallel Processors , Memory Technologies, OS for Multiprogrammed Computer
To Involve Discussions/ Practice/Exercise Onto Revising & Familiarizing the Concepts Acquired Over the 5 Units of the Subject for Improved Employability Skills
UNIT – I THEORY OF PARALLELISM
Parallel Computer Models – the State of Computing-Introduction to Parallel Processing Parallelism in Uniprocessor & Multiprocessors, Parallel Architectural Classification Schemes Speedup Performance Laws- -Program and Network Properties-H/W-S/W Parallelism.
UNIT – II SYSTEM INTERCONNECT ARCHITECTURES
Integration – FPGA Design Flow – Logic Synthesis – LUT Based Technology Mapping – Modeling – Temporal Partitioning Algorithms – Offline and Online Temporal Placement – Managing Device’s Free and Occupied Spaces.
UNIT – III PIPELINING AND SUPERSCALAR TECHNOLOGIES
Pipeline Principle and Implementation-Classification of Pipeline Processor – Introduction of Arithmetic, Instruction, Processor Pipelining-Pipeline Mechanisms-Hazards.
UNIT – IV HARDWARE TECHNOLOGIES
Introduction to Features of Advanced Embedded Processors through basic comparative study: of Architectures -Addressing Modes -Instruction Types performance of- Parallel and Scalable Architectures, Multiprocessor and SIMD, MIMD Computers, RISC, CISC, Superscalar, VLIW , Vector, Systolic Processors of their unique features -scalable, Multithreaded and Dataflow Architectures inter PE Communication-Interconnection Networks- Array & Vector Processors, Vector Instruction Types Performance Modeling-Design of Vectorising Compiler- Case Architecture of Itanium Processor, Pentium Processor, SPARC Processor
UNIT – V OS ISSUES FOR MULTI PROCESSOR
Introduction-Need for Preemptive OS – Synchronising and Scheduling in Multiprocessor OS-, usual OS Scheduling Techniques, Threads – Classification of Multiprocessor OS – Software Requirements of Multiprocessor OS, Distributed Scheduler – PVM – PT Threads in Shared Memory Systems.
TOTAL:45 PERIODS
COURSE OUTCOMES:
At the end of this course, the students will be
CO1: Able to understand the operations of Multiprocessor and Multicomputer Systems.
CO2: Able to understand the various Advanced Processor Technology, Pipelining and Scalable Architectures.
CO3: Able to know the working of Superscalar Pipeline, Cache Memory Organization.
CO4: Able to understand the principles of Multithreading, Multi Thread Architecture, Static and Dynamic Dataflow.
CO5: To improve employability and entrepreneurship capacity due to knowledge upgradation on recent trends in Embedded Systems Design.
REFERENCES
1. Kai Hwang “Advanced Computer Architecture”. Tata Mcgraw Hill
2. Rajiv Chopra, ‘Advanced Computer Architecture” S Chand , 2010
3. John L. Hennessy, David A. Petterson, “Computer Architecture: A Quantitative Approach”, 4thedition, Elsevier, 2007
4. Dezsosima, Terence Fountain, Peter Kacsuk, “Advanced Computer Architecture – A Design space Approach”. Pearson Education,2003.
5. Sajjan G. Shiva “Advanced Computer Architecture”, Taylor & Francis, 2008