ET4071 DSP Based System Design Syllabus:
ET4071 DSP Based System Design Syllabus – Anna University PG Syllabus Regulation 2021
COURSE OBJECTIVES:
1. To understand various representation methods of DSP system
2. To provide insight about different DSP algorithms
3. To familiarize the various architectures of DSP system
4. To perform analysis of DSP architectures and to learn the implementation of DSP system in programmable hardware
5. To learn the details of DSP system interfacing with other peripherls
UNIT I REPRESENTATION OF DSP SYSTEM
Single Core and Multicore, Architectural requirement of DSPs – high throughput, low cost, low power, small code size, embedded applications. Representation of digital signal processing systems – block diagrams, signal flow graphs, data-flow graphs, dependence graphs. Techniques for enhancing computational throughput – parallelism and pipelining.
UNIT II DSP ALGORITHMS
DSP algorithms – Convolution, Correlation, FIR/IIR filters, FFT, adaptive filters, sampling rate converters, DCT, Decimator, Expander and Filter Banks. DSP applications. Computational characteristics of DSP algorithms and applications, Numerical representation of signals-word length effect and its impact, Carry free adders, Multiplier.
UNIT III SYSTEM ARCHITECTURE
Introduction, Basic Architectural Features, DSP Computational Building Blocks, Bus Architecture and Memory, Data Addressing Capabilities, Address Generation Unit, Programmability and Program Execution, Features for External Interfacing. VLIW architecture. Basic performance issue in pipelining, Simple implementation of MIPS, Instruction Level Parallelism, Dynamic Scheduling, Dynamic Hardware Prediction, Memory hierarchy. Study of FIxed point and floating point DSP architectures
UNIT IV ARCHITECTURE ANALYSIS ON PROGRAMMABLE HARDWARE
Analysis of basic DSP Architectures on programmable hardwares. Algorithms for FIR , IIR, Lattice filter structures, architectures for real and complex fast Fourier transforms, 1D/2D Convolutions, Winograd minimal filtering algorithm. FPGA: Architecture, different sub-systems, design flow for DSP system design, mapping of DSP algorithms onto FPGA.
UNIT V SYSTEM INTERFACING
Examples of digital signal processing algorithms suitable for parallel architectures such as GPUs and multiGPUs. Interfacing: Introduction, Synchronous Serial Interface CODE, A CODEC Interface Circuit, ADC interface.
TOTAL : 45 PERIODS
COURSEOUTCOMES:
At the end of this course, the students will have the ability in
CO 1: Evaluate the DSP system using various methods.
CO 2: Design algorithm suitable for different DSP applications.
CO 3: Explain various architectures of DSP system.
CO 4: Implement DSP system in programmable hardware.
CO 5: Build interfacing of DSP system with various peripherals.
REFERENCES
1. Sen M Kuo, Woon Seng S Gan, Digital Signal Processors
2. Digital Signal Processing and Application with C6713 and C6416 DSK, Rulph Chassaing, Worcester Polytechnic Institute, A Wiley Interscience Publication
3. Architectures for Digital Signal Processing, Peter Pirsch John Weily, 2007
4. DSP Processor and Fundamentals: Architecture and Features. Phil Lapsley, JBier, AmitSohan, Edward A Lee; Wiley IEEE Press
5. K. K. Parhi – VLSI Digital Signal Processing Systems – Wiley – 1999.
6. RulphChassaing, Digital signal processing and applications with C6713 and C6416 DSK, Wiley, 2005
7. Keshab K Parhi, VLSI Digital Signal Processing Systems:Design and Implementation, student Edition, Wiley, 1999.
8. Nasser Kehtarnavaz, Digital Signal Processing System Design: LabVIEW-Based Hybrid Programming, Academic Press, 2008