DS4006 DSP Integrated Circuits Syllabus:
DS4006 DSP Integrated Circuits Syllabus – Anna University PG Syllabus Regulation 2021
COURSE OBJECTIVES:
To impart knowledge on fundamental signal processing algorithms and systems.
To expose digital filter concepts, structures and hardware issues.
To understand the various modules used in general purpose digital signal processors.
To introduce various implementation strategies for signal processing algorithms.
To gain knowledge for tuning signal processing algorithms for VLSI.
UNIT I INTRODUCTION TO DSP INTEGRATED CIRCUITS
Sampling of analog signals, Selection of sample frequency, Signal- processing systems, Frequency response, Transfer functions, FFT-The Fast Fourier Transform Algorithm, Discrete cosine transforms, Image coding, Adaptive DSP algorithms, Standard digital signal processors, Application specific IC‟s for DSP, DSP system design, Integrated circuit design
UNIT II DIGITAL FILTERS AND FINITE WORD LENGTH EFFECTS
FIR filters, FIR filter structures, IIR filters, Specifications of IIR filters, Mapping of analog transfer functions, Signal flow graphs, Filter structures, Mapping of analog filter structures, Finite word length effects – Parasitic oscillations, Scaling of signal levels, Round-off noise, Measuring roundoff noise, Coefficient sensitivity, Sensitivity and noise. Multirate systems, Interpolation with an integer factor L, Sampling rate change with a ratio L/M, Multirate filters.
UNIT III DSP ARCHITECTURES
DSP system architectures, Standard DSP architecture-Harvard and Modified Harvard architecture. TMS320C54x and TMS320C6x architecture, Multiprocessors and multicomputers, Systolic and Wavefro
UNIT IV SYNTHESIS OF DSP ARCHITECTURES & ARITHMETIC UNIT
Synthesis: Mapping of DSP algorithms into hardware, Implementation based on complex PEs, Shared memory architecture with Bit – serial PEs. Arithmetic Unit : Conventional number system, Redundant Number system, Residue Number System, Bit-parallel and Bit-Serial arithmetic, Digit Serial arithmetic, CORDIC Algorithm, Basic shift accumulator, Reducing the memory size, Complex multipliers, Improved shift-accumulator
UNIT V CASE STUDY-INTEGRATED CIRCUIT DESIGN
Layout of VLSI circuits, Layout Styles, Case Study : FFT processor, DCT processor and Interpolator.
TOTAL:45 PERIODS
COURSE OUTCOMES:
CO1: Ability to analyze and design fundamental signal processing algorithms and systems.
CO2: Adequacy to design and analyze digital filter concepts and structures.
CO3: Equipped to design general purpose digital signal processors.
CO4: Ability to use various implementation strategies for signal processing algorithms.
CO5: Equipped to design signal processing VLSI systems
REFERENCES:
1. Lars Wanhammer, DSP Integrated Circuits, Academic press, New York, 2012.
2. John J. Proakis, Dimitris G. Manolakis, Digital Signal Processing, Pearson Education, Fourth edition. 2007.
3. Avtar Singh, S.Srinivasan, Digital Signal Processing Implementations: Using DSP Microprocessors (with examples from TMS320C54XX), Thomson Publications, 2004.
4. RulphChassaing , Donald Reay, Digital Signal Processing and Applications with the TMS320C6713 and TMS320C6416 DSK, John Wiley & Sons, 2008.
5. B.Venkatramani, M.Bhaskar, Digital Signal Processors, Tata McGraw-Hill, 2002.
6. KeshabK.Parhi, VLSI Digital Signal Processing Systems design and Implementation, John Wiley & Sons, 2007.