AP4071 Computer Architecture and Parallel Processing Syllabus:
AP4071 Computer Architecture and Parallel Processing Syllabus – Anna University PG Syllabus Regulation 2021
COURSE OBJECTIVES:
Discuss the basic concepts and structure of computers.
Explain the concepts of number representation and arithmetic operations.
Explain different types of Memory architectures.
Describe various parallel processing schemes and vector architecture.
Summarize the Instruction execution stages and Memory hierarchy.
UNIT I INTRODUCTION TO COMPUTER ORGANIZATION
Architecture and function of general computer system – Basic Operational Concepts, Bus Structures, Software Performance – Memory locations & addresses – Memory operations – Instruction and instruction sequencing – addressing modes – assembly language – System buses, Multi-bus organization
UNIT II DATA REPRESENTATION
Signed number representation, fixed and floating point representations, character representation. Computer arithmetic – integer addition and subtraction, ripple carry adder, carry look-ahead adder – multiplication – shift-and-add, Booth multiplier, carry save multiplier – Division – non-restoring and restoring techniques, floating point arithmetic.
UNIT III PROCESSOR ARCHITECTURE AND CONTROL UNIT
A Basic MIPS implementation – Building a Datapath – Control Implementation Scheme – Hardwired control – micro programmed control – Pipelining – Pipelined datapath and control – Handling Data Hazards & Control Hazards – Exceptions. Processor Architecture: Very Long Instruction Word (VLIW) Architecture, Digital Signal Processor Architecture, System on Chip (SoC) architecture, MIPS Processor and programming
UNIT IV PARALLEL PROCESSING
Parallel processing challenges – Flyn’s classification – Single Instruction Single Data (SISD), Multiple Instruction Multiple Data (MIMD), Single Instruction Multiple Data (SIMD), Single Program Multiple Data (SPMD), and Vector Architectures – Hardware multithreading – Multi-core processors and other Shared Memory Multiprocessors – Introduction to Graphics Processing Units, Clusters, Warehouse Scale Computers and other Message-Passing Multiprocessors.
UNIT V MEMORY & I/O SYSTEMS
Memory Hierarchy – memory technologies – cache memory – measuring and improving cache performance – virtual memory, Translation Lookaside Buffers – Accessing I/O Devices – Interrupts – Direct Memory Access – Bus structure – Bus operation – Arbitration – Interface circuits – Universal Serial Bus.
TOTAL: 45 PERIODS
COURSE OUTCOMES
Upon completion of this course, the student will be able to
CO1: Understand the basic organization of computer and different instruction formats and addressing modes. (K2)
CO2: Interpret the representation and manipulation of data on the computer. (K3)
CO3: Illustrate about implementation schemes of control unit and pipeline performance. (K2)
CO4: Summarize the various types of parallelism architectures. (K2)
CO5: Compare the various memory hierarchy and I/O systems. (K2)
REFERENCES
1. David A. Patterson and John L. Hennessy, “Computer Organization and Design: The Hardware/Software Interface”, Morgan Kaufmann / Elsevier, 5th Edition, 2014.
2. Carl Hamacher, ZvonkoVranesic, SafwatZaky and Naraig Manjikian, “Computer Organization and Embedded Systems”, Tata McGraw Hill, 6th Edition, 2012.
3. William Stallings, “Computer Organization and Architecture – Designing for Performance”, Pearson Education, 8th Edition, 2010.
4. John P. Hayes, “Computer Architecture and Organization”, Tata McGraw Hill, 3rd Edition, 2012.
5. John L. Hennessey and David A. Patterson, “Computer Architecture – A Quantitative Approach”, Morgan Kaufmann / Elsevier Publishers, 5th Edition, 2012.