DS4005 Signal Integrity for High Speed IC Design Syllabus:
DS4005 Signal Integrity for High Speed IC Design Syllabus – Anna University PG Syllabus Regulation 2021
COURSE OBJECTIVES:
To identify sources affecting the speed of digital circuits.
To introduce methods to improve the signal transmission characteristics.
To identify the power consideration factor during the system design
UNIT I SIGNAL PROPAGATION ON TRANSMISSION LINES
Transmission line equations, wave solution, wave vs. circuits, initial wave, delay time, Characteristic impedance , wave propagation, reflection, and bounce diagrams Reactive terminations – L, C , static field maps of micro strip and strip line cross-sections, per unit length parameters, PCB layer stackups and layer/Cu thicknesses, cross-sectional analysis tools, Zo and Td equations for microstrip and stripline Reflection and terminations for logic gates, fan-out, logic switching , input impedance into a transmission-line section, reflection coefficient, skin-effect, dispersion.
UNIT II MULTI-CONDUCTOR TRANSMISSION LINES AND CROSSTALK
Multi-conductor transmission-lines, coupling physics, per unit length parameters ,Near and far-end cross-talk, minimizing cross-talk (strip line and microstrip) Differential signalling, termination, balanced circuits ,S-parameters, Lossy and Lossless models
UNIT III NON-IDEAL EFFECTS
Non-ideal signal return paths – gaps, BGA fields, via transitions , Parasitic inductance and capacitance , Transmission line losses – Rs, tanδ , routing parasitic, Common-mode current, differential-mode current , Connectors
UNIT IV POWER CONSIDERATIONS AND SYSTEM DESIGN
SSN/SSO , DC power bus design , layer stack up, SMT decoupling ,, Logic families, power consumption, and system power delivery , Logic families and speed Package types and parasitic ,SPICE, IBIS models ,Bit streams, PRBS and filtering functions of link-path components , Eye diagrams , jitter , inter-symbol interference Bit-error rate ,Timing analysis.
UNIT V CLOCK DISTRIBUTION AND CLOCK OSCILLATORS
Timing margin, Clock slew, low impedance drivers, terminations, Delay Adjustments, canceling parasitic capacitance, Clock jitter.
TOTAL:45 PERIODS
COURSE OUTCOMES:
CO1: Identify the wave propagation in transmission line to find sources affecting the speed of digital circuits.
CO2: Identify methods to improve the signal transmission characteristics
CO3:Identify methods to recover non-ideal effects
CO4:Analyze fundamental power considerations and system design
CO5:Understand the various modules clock distribution and clock oscillators
REFERENCES:
1. H. W. Johnson and M. Grahm, High Speed Digital Design:A hand book of Black Magic, Prentice Hall, 1 edition 2003.
2. John D Ryder, Networks lines and field”, Prentice Hall of India, 2nd edition 2015
3. Douglas Brooks, Signal Integrity Issues and Printed Circuit Board Design, Prentice Hall PTR , 2012.
4. S. Hall, G. Hall, and J. McCall, High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices, Wiley-Interscience, 2014.
5. Eric Bogatin , Signal Integrity – Simplified , Prentice Hall PTR, 2003.
TOOLS REQUIRED
1. SPICE, source – http://www-cad.eecs.berkeley.edu/Software/software.html
2.HSPICE from synopsis, www.synopsys.com/products/mixedsignal/hspice/hspice.html
3. SPECCTRAQUEST from Cadence, http://www.specctraquest.com