AP4010 Modeling and Synthesis with HDL Syllabus:
AP4010 Modeling and Synthesis with HDL Syllabus – Anna University PG Syllabus Regulation 2021
COURSE OBJECTIVES:
To know the basic language features of Verilog HDL and its the role in digital logic design.
To know the behavioural modeling of combinational and sequential circuits.
To know the behavioural modeling of algorithmic state machines.
To know the synthesis of combinational and sequential descriptions.
To know the architectural features of programmable logic devices.
UNIT I INTRODUCTION TO LOGIC DESIGN WITH VERILOG
Overview of Digital Design with Verilog HDL – Hierarchical Modeling Concepts: Top-down and bottom-up design methodology, differences between modules and module instances, parts of a simulation, design block, stimulus block – Basic Concept- Modules and Ports: Module definition, port declaration, connecting ports, hierarchical name referencing. Tasks and Functions
UNIT II LEVELS OF MODELING
Gate-Level Modeling :Modeling using basic Verilog gate primitives, description of and/or and buf/not type gates, rise, fall and turn-off delays, min, max, and typical delays. Dataflow Modeling: Continuous assignments, delay specification, expressions, operators, operands, operator types. Behavioral Modeling: Structured procedures, initial and always, blocking and nonblocking statements, delay control, generate statement, event control, conditional statements, multiway branching, loops, sequential and parallel blocks.
UNIT III DESIGN OF DIGITAL LOGIC USING HDL
Design of combinational logic: adders, multiplexers, de-multiplexers, encoders and decoders, comparators, multipliers – Design of Sequential logic : Flip-flops, synchronous and Asynchronous counters, shift registers, Universal shift register, FSM and LFSR. (Using various Levels of Modeling)
UNIT IV LOGIC SYNTHESIS AND DESIGN FLOW
Logic Synthesis with verilog HDL-Synthesis Design flow, RTL and Test Bench Modeling Techniques and Timing and Path Delay Modeling, Timing Checks, Switch Level Modeling
UNIT V PROGRAMMABLE LOGIC DEVICES
Programmable logic devices, storage devices, programmable logic array programmable array logic, programmability of PLDs CPLDs.
TOTAL: 45 PERIODS
PRACTICAL EXERCISES: 30 PERIODS
1. Design Entry Using VHDL Or Verilog Using HDL Languages of
I. Combinational Circuits Namely 8:1 Mux/Demux, Full Adder, 8-Bit Magnitude Comparator, Encoder/Decoder, Priority Encoder.
II. Sequential Circuits Namely D-FF, 4-Bit Shift Registers (SISO, SIPO, PISO, Bidirectional), 3-Bit Synchronous Counters.
2. Test Vector Generation And Timing Analysis of Sequential And Combinational Logic Design for exercise (1) above.
2. Synthesis, P&R and Post P&R Simulation of the Components Simulated In (1) Above.
3. FPGA Implementation of PCI Bus & Arbiter.
Verifying Design Functionality Using Either Chipscope Feature (Xilinx) /the Signal Tap Feature (Altera)/Other Equivalent Feature . Invoke the PLL And Demonstrate the Use of the PLL Module for Clock Generation in FPGAs.
COURSE OUTCOMES:
After successful completion of the course, the students are able to
CO1: demonstrate knowledge on HDL design flow and digital circuits design.
CO2:design and develop the combinational and sequential circuits using various modeling
CO3:solving algorithmic state machines using hardware description language
CO4:analyze the process of synthesizing the combinational and sequential descriptions
CO5:know the advantages of programmable logic devices and their description in Verilog
TOTAL : 45 +30=75 PERIODS
REFERENCES
1. Samir Palnitkar – Verilog HDL, 2nd edition, Pearson Education, 2003.
2. Michael D Ciletti – Advanced Digital Design with the VERILOG HDL, 2ND Edition, PHI, 2009.
3. Z Navabi – Verilog Digital System Design, 2nd Edition, McGraw Hill, 2005.
4. Stephen Brown and Zvonko Vranesic – Fundamentals of Digital Logic with Verilog, 2nd Edition, TMH, 2008.